1. Field of the Invention
The present invention relates to a two-step parallel A/D converter converting an analog signal to a digital signal, and more particularly, it relates to a technology directed to enhance an accuracy of an A/D converter and improvement of a differential amplifier utilized therefore.
2. Description of the Prior Art
FIG. 5 is a block diagram showing an exemplary two-step parallel A/D converter in the prior art as described in IEEE Journal of Solid-State Circuits, vol.24, No.1, Feb. 1989, pp. 13-20. Referring to FIG. 5, the A/D converter includes an input terminal 4c for receiving an analog signal, a sample-and-hold circuit 6 (referred to as "S/H circuit" hereinafter) for sampling an instantaneous value of a sequentially varying analog signal and holding it for a specified period of time, a positive reference voltage terminal 7a and a negative reference voltage terminal 7b,a group 8a of resistances connected in series between the reference voltage terminals 7a and 7b for dividing coarse A/D conversion reference voltage to perform A/D conversion of high-order digits (i.e., upper bits), a group 9a of comparators which have their respective first input: terminals receiving an input signal from the input terminal 4c and second input terminals connected to the resistance group 8a respectively, for comparing respectively the divided coarse A/D conversion reference voltage with voltage of the input signal to perform A/D conversion of the high-order digits, a D/A converter 10 receiving an output from each comparator of the comparator group 9a for converting a digital signal of the high-order digits (i.e., a coarse digital signal) into an analog signal, and a resistance 8d connected to the D/A converter 10 for outputting the analog signal corresponding to the coarse digital signal.
The prior art two-step parallel A/D converter further includes a resistance 8e connected to the D/A converter 10 for converting constant current produced by the D/A converter 10 into voltage, a first differential amplifier 11c having its first input terminal connected to one of terminals of the resistance 8d and its second input terminal connected to an output terminal of the S/H circuit 6 for amplifying difference voltage obtained by subtracting voltage of an analog signal D2 corresponding to the coarse digital signal from voltage of an input signal D1 to output the resultant voltage from its first output terminal, a second differential amplifier 11b having its first and second input terminals connected to opposite first and second terminals of the resistance 8e for outputting reference voltage from its first and second output terminals, a group 8b of resistances connected in series between the first and second output terminals of the second differential amplifier 11b for dividing fine A/D conversion reference voltage, a group 9b of comparators which have their respective first input terminals receiving an output from the first differential amplifier 11 c and second input terminals connected to the resistances of group 8b respectively for comparing respectively the divided fine A/D conversion reference voltage with the output from the first differential amplifier 11b or the amplified difference voltage obtained by subtracting the voltage of the analog signal D2 from the voltage of the input signal D1 to perform A/D conversion of low-order digits (i.e., lower bits), an encode circuit 12a receiving an output from each comparator of the comparator group 9a to encode the output digital signal of high-order digits, an encode circuit 12b for receiving an output from each comparator of the comparator group 9a to encode the output digital signal of low-order digits, an adder 13 for receiving output signals from the encode circuits 12a and 12b to add them, an output terminal 15 connected to an output terminal of the adder 13 for outputting a coded digital signal, and a constant current source 16 for supplying constant current to the resistance 8e. The resistance group 8a and the comparator group 9a constitute a coarse A/D converting unit for obtaining high-order digits of digital signals, and the resistance group 8b and the comparator group 9b constitute a fine A/D converting unit for obtaining low-order digits of digital signals (i.e., fine digital signals).
An operation of the A/D converter shown in FIG. 5 will now be described. This converter is a two-step parallel A/D converter which includes a coarse A/D converting unit for performing A/D conversion of high-order digits and a fine A/D converting unit for performing A/D conversion of low-order digits to perform A/D conversion of an analog input signal input thereto twice to convert it into a digital signal.
An analog signal received from the input terminal 4c is sampled and held by the S/H circuit 6. The analog signal D1 held by the S/H circuit 6 is transmitted to each comparator of the comparator group 9a. Coarse A/D conversion reference voltage applied to the reference voltage terminals 7a and 7b is divided by the resistance group 8a and each of them transferred to each comparator of the comparator group 9a respectively. Then, in each comparator of the comparator group 9a, the first comparison of the divided coarse A/D conversion reference voltage with the analog signal D1 is performed, and a result of the comparison is transmitted to the encode circuit 12a and the D/A converter 10. In the encode circuit 12a, the digital signal of the high-order digits is coded and then output to the adder 13. The D/A converter 10 converts the coarse digital signal input thereto into the analog signal D2 and then transmit it to the first differential amplifier 11e serving as a subtracter.
The first differential amplifier 11c subtracts the analog signal D2 output from the D/A converter 10 from the analog signal D1 output by the S/H circuit 6. Voltage of the difference obtained by subtraction of the analog signal D2 from the analog signal D1 is transmitted to the fine A/D converting unit, and the second comparison is performed. The difference voltage output from the first output terminal of the first differential amplifier 11c is transmitted to the comparator group 9b and applied to the first input terminal of each comparator. The fine A/D conversion reference voltage output by the second differential amplifier 11b is divided by the resistance group 8b and then input to the second input terminal of each comparator of the comparator group 9b, respectively. Then, each comparator of the comparator group 9a compares the divided fine A/D conversion reference voltage with the difference voltage and transmits a result of comparison to the encode circuit 12b. The encode circuit 12b converts the result of the comparison in the comparator group 9b into digital data to output it to the adder 13. The adder 13 adds output data from the coarse and fine A/D converting units, corrects a result, and produce a desired digital output.
A differential amplifier used in the A/D converter or the like as illustrated in FIG. 5 will now be described. FIG. 4 is a circuit diagram showing an exemplary differential amplifier in the prior art as described in "Transistor Technology" Dec. 1990, p.512, FIG. 2(a). Referring to FIG. 4, the differential amplifier includes NPN bipolar transistors, Q1 to Q4, emitter resistances 2a and 2b and collector resistances 2c and 2d respectively connected to emitter electrodes and collector electrodes of the NPN bipolar transistors Q1 and Q2, constant current sources, 3a to 3d, for outputting constant current I.sub.0, first and second input terminals 4a and 4b receiving input voltage applied to the differential amplifier, and first and second output terminals 5a and 5b of the differential amplifier.
An operation of the differential amplifier will be described below. The differential amplifier amplifies a difference between voltages applied to the first and second input terminals 4a and 4b. For example, assuming that voltage applied to the first input terminal 4a (a base electrode of the NPN bipolar transistor Q1) is V.sub.1 and voltage applied to the second input terminal 4b (a base electrode of the NPN bipolar transistor Q2) is V.sub.2, output voltages V.sub.01 and V.sub.02 from the first and second output terminals 5a and 5b will now be found.
First note the current flowing in portions communicating emitters of the NPN bipolar transistors Q1 and Q2. The input voltages V.sub.1 and V.sub.2 are reduced by base-emitter voltages V.sub.BE1 and V.sub.BE2 of the NPN bipolar transistors Q1 and Q2, respectively. Assuming now that a resistance value of a pair of the emitter resistances 2a and 2b is R.sub.E, current I.sub.RE expressed in Formula 1 as follows flows in the emitter resistances 2a and 2b: ##EQU1## Thus, both the current derived from the constant current source and the current caused by the potential difference between the emitter resistances 2a and 2b flow in the emitter electrode of the NPN bipolar transistor Q1; that is, a value of emitter current of the NPN bipolar transistor Q1 can be expressed by I.sub.O +I.sub.RE. Also, both the current derived from the constant current source 3c and the current caused by the emitter resistances 2a and 2b flow in the emitter electrode of the NPN bipolar transistor Q2; that is, a value of emitter current of the NPN bipolar transistor Q2 is expressed by I.sub.O -I.sub.RE.
Collector currents I.sub.C1 and I.sub.C2 of the NPN bipolar transistors Q1 and Q2 are given by the following Formula 2 and Formula 3, assuming that a current amplification factor is .alpha..sub.0 (almost equal to 1): EQU I.sub.C1 =.alpha..sub.0 I.sub.E1 .apprxeq.(I.sub.0 +I.sub.RE)(2) EQU I.sub.C2 =.alpha..sub.0 I.sub.E2 .apprxeq.(I.sub.0 -I.sub.RE)(3)
The output voltages V.sub.01 and V.sub.02 are expressed with base-emitter voltages V.sub.BE3 and V.sub.BE4 of the NPN bipolar transistors Q3 and Q4 by the following Formula 4 and Formula 5: EQU V.sub.01 =V.sub.CC -R.sub.C I.sub.C1 -V.sub.BE3 =V.sub.CC -R.sub.C (I.sub.0 +I.sub.RE)-V.sub.BE3 ( 4) EQU V.sub.02 =V.sub.CC -R.sub.C I.sub.C2 -V.sub.BE4 =V.sub.CC -R.sub.C (I.sub.0 -I.sub.RE)-V.sub.BE4 ( 5)
Herein, however, base currents of the NPN bipolar transistors Q3 and Q4 are ignored. Thus, voltage between the output terminals 5a and 5b of the differential amplifier is expressed in Formula 6: ##EQU2##
If it is assumed that the NPN bipolar transistors, Q1 to Q4, are all identical in feature although it is an ideal case, and without considering the difference between the collector currents I.sub.C1 and I.sub.C2, the base-emitter voltages, V.sub.BE1 to B.sub.BE4, are all equivalent to one another, and the difference of the output voltages (V.sub.01 -V.sub.02) in such a case is given by the following Formula 7: EQU V.sub.01 -V.sub.02 =-R.sub.C /R.sub.E (V.sub.1 -V.sub.2) (7)
Thus, it is apparent that the differential amplifier shown in FIG. 4 can amplify the difference between the voltages applied to the two input terminals 4a and 4b with a resistance rate of the collector resistances 2c and 2d to the emitter resistances 2a and 2b.
The prior art differential amplifier configured as mentioned above has disadvantages as discussed below:
The difference of the output voltages (V.sub.01 -V.sub.02) as expressed in Formula 7 is obtained under the requirements that the collector currents I.sub.C1 and I.sub.C2 are equal to each other and that the transistors are all identical in feature. However, the base-emitter voltage V.sub.BE is expressed by a non-linear equation as in Formula 8. "1n" hereinafter represents a natural logarithm. EQU V.sub.BE =V.sub.T .multidot.1n(I.sub.C /I.sub.S) (8)
where V.sub.T is thermoelectric voltage and I.sub.S is saturation current. As can be seen in Formula 6, as the base-emitter voltages, V.sub.BE1 to V.sub.BE4, of the NPN bipolar transistors, Q1 to Q4, vary, the difference of the output voltages (V.sub.01 -V.sub.02) varies. Thus, a gain (an amplification degree) of the differential amplifier is reduced, and linearity is degraded from the non-linear property of the base-emitter voltage V.sub.BE. Furthermore, in practice, it is unattainable that all the transistors are identical in feature because of variations in the process of manufacturing them. This also causes the base-emitter voltages, V.sub.BE1 to V.sub.BE4, to vary from one to another.
The prior art two-step parallel A/D converter configured as mentioned above has disadvantages as follows:
FIG. 6 is a circuit diagram showing the first and second differential amplifiers 11c and 11b constituting the A/D converter shown in FIG. 5. FIG. 6(a) depicts the first differential amplifier 11c which is an input stage of a fine A/D converting unit, and FIG. 6(b) depicts the second differential amplifier 11b which is a reference stage of the fine A/D converting unit. Referring to FIG. 6, the differential amplifiers include differential amplifying elements DA1 and DA2, NPN bipolar transistors, Q3a, Q3b, Q4a and Q4b,constituting emitter followers, and a resistance r1. The NPN bipolar transistors, Q3a, Q3b, Q4a and Q4b,have their respective collector electrodes connected to power sources and their respective emitter electrodes connected to constant current sources for outputting constant current I.sub.EO. In the differential amplifiers, base-emitter voltages of the above transistors, namely, V.sub.be1 of each of the NPN bipolar transistors Q3a and Q3b, and V.sub.be2 of each of the NPN bipolar transistors Q4a and Q4b, are given by Formulas 9, 10 and 11 as follows: EQU Input Stage: V.sub.be1 =V.sub.T .multidot.1n(.alpha.I.sub.E0 /I.sub.S)(9) EQU Reference Stage: V.sub.be1 =V.sub.T .multidot.1n{.alpha.(I.sub.E0 +I.sub.R)/I.sub.S } (10) EQU V.sub.be2 =V.sub.T .multidot.1n{.alpha.(I.sub.E0 -I.sub.R)/I.sub.S }(11)
where .alpha. is a current amplification factor and I.sub.EO is a value of current flowing in the constant current sources. Hence, output voltage V.sub.O of the first and second differential amplifiers 11c and 11b are given by the following Formula 12 and Formula 13: ##EQU3##
As can be seen, the output voltage V.sub.O varies from the input stage to the reference stage; that is, comparing the left side of Formula 13 with that of Formula 12, it will be recognized that they include different terms V.sub.b2 and V.sub.be2 from each other. Thus, errors are caused in the outputs for different reasons. In comparing the voltage from the input stage (the output voltage from the first differential amplifier 11c) with the voltage from the output stage (the output voltage from the second differential amplifier 11b) by the comparators of the fine A/D converting unit, sometimes there arises the problem of mismatch; i.e., those which are different in output range are compared.